71. Grams. S. Lin and you can J. B. Kuo, “Fringing-Induced Thin-Channel-Impact (FINCE) Relevant Capacitance Choices away from Nanometer FD SOI NMOS Devices Playing with Mesa-Separation Thru three dimensional Simulation” , EDSM , Taiwan ,

72. J. B. Kuo, “Progression of Bootstrap Techniques in Lower-Voltage CMOS Electronic VLSI Circuits getting SOC Apps” , IWSOC , Banff, Canada ,

P. Yang, “Door Misalignment Effect Relevant Capacitance Behavior out of a great 100nm DG FD SOI NMOS Unit having letter+/p+ Poly Best/Bottom Door” , ICSICT , Beijing, China

73. Grams. Y. Liu, Letter. C. Wang and you may J. B. Kuo, “Energy-Effective CMOS Large-Weight Driver Routine with the Subservient Adiabatic/Bootstrap (CAB) Way of Low-Electricity TFT-Lcd Program Software” , ISCAS , Kobe, Japan ,

74. Y. S. Lin, C. H. Lin, J. B. Kuo and you can K. W. Su, “CGS Capacitance Event of 100nm FD SOI CMOS Gizmos with HfO2 High-k Gate Dielectric Offered Straight and Fringing Displacement Consequences” , HKEDSSC , Hong-kong ,

75. J. B. KUo, C. H. Hsu and you may C. P. Yang, “Gate-Misalignment Related Capacitance Conclusion regarding a great 100nm DG SOI MOS Products with Letter+/p+ Top/Base Entrance” , HKEDSSC , Hong kong ,

76. G. Y. Liu, N. C. Wang and you may J. B. Kuo, “Energy-Productive CMOS Large-Stream Driver Routine to the Subservient Adiabatic/Bootstrap (CAB) Way of Low-Fuel TFT-Liquid crystal display System Programs” , ISCAS , Kobe, The japanese ,

77. H. P. Chen and you may J. B. Kuo, “A beneficial 0.8V CMOS TSPC Adiabatic DCVS Reason Routine to your Bootstrap Technique getting Lower-Power VLSI” , ICECS , Israel ,

B. Kuo, “A book 0

80. J. B. Kuo and H. P. Chen, “A reduced-Current CMOS Stream Rider for the Adiabatic and you may Bootstrap Strategies for Low-Power Program Applications” , MWSCAS , Hiroshima, Japan ,

83. Yards. T. Lin, E. C. Sunlight, and you can J. B. Kuo, “Asymmetric Door Misalignment Influence on Subthreshold Features DG SOI NMOS Products Given Fringing Electric Field-effect” , Electron Devices and you can Material Symposium ,

84. J. B. Kuo, Age. C. Sunshine, and you can Meters. T. Lin, “Studies regarding Gate Misalignment Influence salvadorian women dating on new Threshold Voltage out of Double-Gate (DG) Ultrathin FD SOI NMOS Gadgets Playing with a compact Design Considering Fringing Electronic Field effect” , IEEE Electron Gizmos to possess Microwave and you will Optoelectronic Apps ,

86. E. Shen and you may J. 8V BP-DTMOS Stuff Addressable Memories Cell Circuit Produced by SOI-DTMOS Techniques” , IEEE Meeting for the Electron Gadgets and you can Solid state Circuits , Hong-kong ,

87. P. C. Chen and you will J. B. Kuo, “ic Logic Circuit Having fun with a primary Bootstrap (DB) Way of Lower-voltage CMOS VLSI” , All over the world Symposium towards the Circuits and you may Options ,

89. J. B. Kuo and you will S. C. Lin, “Lightweight Dysfunction Design to have PD SOI NMOS Equipment Considering BJT/MOS Effect Ionization to own Liven Circuits Simulation” , IEDMS , Taipei ,

ninety. J. B. Kuo and S. C. Lin, “Compact LDD/FD SOI CMOS Device Model Considering Time Transportation and you can Care about Heat getting Liven Routine Simulation” , IEDMS , Taipei ,

91. S. C. Lin and you will J. B. Kuo, “Fringing-Induced Burden Reducing (FIBL) Aftereffects of 100nm FD SOI NMOS Equipment with a high Permittivity Entrance Dielectrics and LDD/Sidewall Oxide Spacer” , IEEE SOI Meeting Proc , Williamsburg ,

ninety-five. J. B. Kuo and you may S. C. Lin, “Brand new Fringing Electronic Field effect towards Short-Route Effect Threshold Current of FD SOI NMOS Products that have LDD/Sidewall Oxide Spacer Construction” , Hong-kong Electron Equipment Appointment ,

93. C. L. Yang and you will J. B. Kuo, “High-Temperature Quasi-Saturation Model of Highest-Current DMOS Electricity Products” , Hong kong Electron Gizmos Appointment ,

94. Age. Shen and you may J. B. Kuo, “0.8V CMOS Stuff-Addressable-Memories (CAM) Telephone Ciurcuit that have a quick Mark-Compare Possibilities Using Bulk PMOS Dynamic-Endurance (BP-DTMOS) Method Predicated on Basic CMOS Technology getting Reduced-Current VLSI Systems” , Worldwide Symposium for the Circuits and you will Expertise (ISCAS) Proceedings , Washington ,